TSMC mass production of 3-nm chips starts in 2022
|After the 5-nm norm, the next important process for TSMC will be 3 nm. According to the Taiwanese manufacturer, research and development of its 3-nm process technology is progressing according to schedule. The company recently announced that it will launch trial production in 2021. However, large-scale mass printing should begin in the second half of 2022. |
Although it is still almost two years before TSMC's 3-nanometer process enters the mass production stage, many of its customers are already interested in these advanced standards. It is reported that TSMC is preparing four waves of deployment of 3-nm production capacity. The lion's share of the first wave will be transferred to Apple, which is quite expected. Starting with the A10 processor in the 2016 iPhone 7 smartphone series, Apple's A-series processors are manufactured exclusively at TSMC and are always given priority.
The 3-nm process should significantly improve the performance and energy efficiency of the chips. At meetings dedicated to the company's financial reports in the first and second quarters of this year, TSMC Executive Director Wei Zhejia said that compared to the 5-nm process, 3-nm standards will increase the density of transistors by 70%, as well as increase the frequency of chips by 10-15% with the same power consumption. In turn, energy efficiency at the same frequencies will increase by 25-30 %.
According to the Taiwan Economic Daily, TSMC has already made a big breakthrough in the development of the 2-nm process. The research and development process is now at an advanced stage. The company is optimistic that in the second half of 2023, the number of usable crystals in its trial 2-nm production can reach 90 %. Supply chains also show that, unlike the 3-nm and 5-nm processes that use FinFET, the 2-nm TSMC process uses a new architecture of MBCFET (Multi Bridge Channel FET) field-effect transistors, in which the transistor channel will look like several channels located on top of each other in the form of nanostreads surrounded on all sides by a gate (you can read about these transistors performed by Samsung in our article for March 14, 2019).
Last year, TSMC set up a 2-NMR research and development team to find the best way forward. Using MBCFET will overcome the physical current leakage limit for FinFET volume transistors. TSMC previously reported that its 2-nm process development will be performed in Baoshan and Hsinchu. It also plans to build four huge P1–P4 plants for the production of ultra-large silicon wafers (450 mm in diameter) on an area of more than 90 hectares. If we take into account the current progress in research and development of 2-nm TSMC standards, the company should enter mass production in 2024.
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